391 search results - page 46 / 79 » Massively parallel processing on a chip |
IJHPCA
2010
13 years 6 months ago
2010
With processor speeds no longer doubling every 18-24 months owing to the exponential increase in power consumption and heat dissipation, modern HEC systems tend to rely lesser on ...
IPPS
1999
IEEE
13 years 12 months ago
1999
IEEE
Abstract. The combination of a language with ne-grain implicit parallelism and a data
ow evaluation scheme is suitable for high-level programming on massively parallel architectur...
MICRO
1992
IEEE
13 years 11 months ago
1992
IEEE
This paper describes a single chip Multiple Instruction Stream Computer (MISC) capable of extracting instruction level parallelism from a broad spectrum of programs. The MISC arch...
IAJIT
2010
13 years 6 months ago
2010
: A new code sign implementation of vector median rational hybrid filter based on efficient hardware/software implementation is introduced and applied to colour image filtering pro...
ICCCN
2008
IEEE
14 years 2 months ago
2008
IEEE
—Understanding the communication behavior and network resource usage of parallel applications is critical to achieving high performance and scalability on systems with tens of th...