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» Massively parallel processing on a chip
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IPPS
2007
IEEE
14 years 2 months ago
Software and Algorithms for Graph Queries on Multithreaded Architectures
Search-based graph queries, such as finding short paths and isomorphic subgraphs, are dominated by memory latency. If input graphs can be partitioned appropriately, large cluster...
Jonathan W. Berry, Bruce Hendrickson, Simon Kahan,...
ICPP
2006
IEEE
14 years 1 months ago
Data Sharing Pattern Aware Scheduling on Grids
These days an increasing number of applications, especially in science and engineering, are dealing with a massive amount of data; hence they are dataintensive. Bioinformatics, da...
Young Choon Lee, Albert Y. Zomaya
SIGMOD
2012
ACM
288views Database» more  SIGMOD 2012»
11 years 10 months ago
Exploiting MapReduce-based similarity joins
Cloud enabled systems have become a crucial component to efficiently process and analyze massive amounts of data. One of the key data processing and analysis operations is the Sim...
Yasin N. Silva, Jason M. Reed
ICCAD
2008
IEEE
147views Hardware» more  ICCAD 2008»
14 years 4 months ago
Overlay aware interconnect and timing variation modeling for double patterning technology
— As Double Patterning Technology (DPT) becomes the only solution for 32-nm lithography process, we need to investigate how DPT affects the performance of a chip. In this paper, ...
Jae-Seok Yang, David Z. Pan
CHES
2007
Springer
111views Cryptology» more  CHES 2007»
14 years 1 months ago
TEC-Tree: A Low-Cost, Parallelizable Tree for Efficient Defense Against Memory Replay Attacks
Replay attacks are often the most costly attacks to thwart when dealing with off-chip memory integrity. With a trusted System-on-Chip, the existing countermeasures against replay r...
Reouven Elbaz, David Champagne, Ruby B. Lee, Lione...