391 search results - page 72 / 79 » Massively parallel processing on a chip |
ASAP
2008
IEEE
14 years 2 months ago
2008
IEEE
As semiconductor processing technology continues to scale down, managing reliability becomes an increasingly difficult challenge in high-performance microprocessor design. Transie...
ASAP
2005
IEEE
14 years 1 months ago
2005
IEEE
Users expect future handhelddevices to provide extended multimedia functionality and have long battery life. This type of application imposes heavy constraints on performance and ...
DFT
2003
IEEE
14 years 1 months ago
2003
IEEE
The implementation of imaging arrays for System-On-a-Chip (SOC) is aided by using faulttolerant light sensors. Fault-tolerant redundancy in an Active Pixel Sensor (APS) is obtaine...
VLSID
2000
IEEE
14 years 2 days ago
2000
IEEE
Digital images are convenient media for describing and storing spatial, temporal, spectral, and physical components of information contained in a variety of domains(e.g. aerial/sa...
PDPTA
2000
13 years 9 months ago
2000
The paper focuses on coarse-grained dynamically reconfigurable array architectures promising performance and flexibility for different challenging application areas, e. g. future ...