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ERSA
2007
177views Hardware» more  ERSA 2007»
13 years 8 months ago
Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors
- Even though state-of-the-art FPGAs present new opportunities in exploring low-cost high-performance architectures for floating-point scientific applications, they also pose serio...
Xiaofang Wang, Sotirios G. Ziavras, Jie Hu
HPCC
2007
Springer
13 years 11 months ago
An Exploration of Performance Attributes for Symbolic Modeling of Emerging Processing Devices
Vector, emerging (homogenous and heterogeneous) multi-core and a number of accelerator processing devices potentially offer an order of magnitude speedup for scientific application...
Sadaf R. Alam, Nikhil Bhatia, Jeffrey S. Vetter
SASP
2009
IEEE
291views Hardware» more  SASP 2009»
14 years 2 months ago
FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs
— As growing power dissipation and thermal effects disrupted the rising clock frequency trend and threatened to annul Moore’s law, the computing industry has switched its route...
Alexandros Papakonstantinou, Karthik Gururaj, John...
IISWC
2008
IEEE
14 years 1 months ago
Characterizing and improving the performance of Intel Threading Building Blocks
Abstract— The Intel Threading Building Blocks (TBB) runtime library [1] is a popular C++ parallelization environment [2][3] that offers a set of methods and templates for creatin...
Gilberto Contreras, Margaret Martonosi
GECCO
2004
Springer
179views Optimization» more  GECCO 2004»
14 years 23 days ago
An Evolutionary Meta Hierarchical Scheduler for the Linux Operating System
Abstract. The need for supporting CSCW applications with heterogeneous and varying user requirements calls for adaptive and reconfigurable schedulers accommodating a mixture of re...
Horst Wedde, Muddassar Farooq, Mario Lischka