Sciweavers

1095 search results - page 201 / 219
» Measuring the Performance of Parallel Message-Based Process ...
Sort
View
DATE
2010
IEEE
195views Hardware» more  DATE 2010»
13 years 10 months ago
Cool MPSoC programming
Abstract--This paper summarizes a special session on multicore/multi-processor system-on-chip (MPSoC) programming challenges. Wireless multimedia terminals are among the key driver...
Rainer Leupers, Lothar Thiele, Xiaoning Nie, Bart ...
ICDCS
2005
IEEE
14 years 1 months ago
ReDAL: Request Distribution for the Application Layer
Modern application infrastructures are based on clustered, multi-tiered architectures, where request distribution occurs in two sequential stages: over a cluster of web servers, a...
Debra E. VanderMeer, Helen M. Thomas, Kaushik Dutt...
ECAI
2004
Springer
14 years 1 months ago
IPSS: A Hybrid Reasoner for Planning and Scheduling
In this paper we describe IPSS (Integrated Planning and Scheduling System), a domain independent solver that integrates an AI heuristic planner, that synthesizes courses of actions...
María Dolores Rodríguez-Moreno, Ange...
HPDC
2010
IEEE
13 years 9 months ago
MOON: MapReduce On Opportunistic eNvironments
MapReduce offers a flexible programming model for processing and generating large data sets on dedicated resources, where only a small fraction of such resources are every unavaila...
Heshan Lin, Xiaosong Ma, Jeremy S. Archuleta, Wu-c...
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
13 years 6 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt