1095 search results - page 40 / 219 » Measuring the Performance of Parallel Message-Based Process ... |
DAC
1997
ACM
13 years 12 months ago
1997
ACM
A methodology for architecture exploration of look-up table based decoders is presented. For the degree of parallel processing a trade-off can be made by exploring system level an...
DAC
2010
ACM
13 years 11 months ago
2010
ACM
With the end of clock-frequency scaling, parallelism has emerged as the key driver of chip-performance growth. Yet, several factors undermine efficient simultaneous use of onchip ...
EUROPAR
2006
Springer
13 years 11 months ago
2006
Springer
There is a large range of image processing applications that act on an input sequence of image frames that are continuously received. Throughput is a key performance measure to be ...
ICS
2003
Tsinghua U.
14 years 1 months ago
2003
Tsinghua U.
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks. Our architecture ass...
ICS
2009
Tsinghua U.
14 years 2 months ago
2009
Tsinghua U.
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...