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ISCAS
2005
IEEE
124views Hardware» more  ISCAS 2005»
14 years 1 months ago
Parallel FFT computation with a CDMA-based network-on-chip
— Fast Fourier transform (FFT) algorithms are used in a wide variety of digital signal processing applications and many of these require high-performance parallel implementations...
Daewook Kim, Manho Kim, Gerald E. Sobelman
IEEEPACT
2002
IEEE
14 years 24 days ago
Effective Compilation Support for Variable Instruction Set Architecture
Traditional compilers perform their code generation tasks based on a fixed, pre-determined instruction set. This paper describes the implementation of a compiler that determines ...
Jack Liu, Timothy Kong, Fred C. Chow
PVM
2005
Springer
14 years 1 months ago
A Peer-to-Peer Framework for Robust Execution of Message Passing Parallel Programs on Grids
Abstract. This paper presents P2P-MPI, a middleware aimed at computational grids. From the programmer point of view, P2P-MPI provides a message-passing programming model which enab...
Stéphane Genaud, Choopan Rattanapoka
ISCA
1999
IEEE
88views Hardware» more  ISCA 1999»
14 years 4 days ago
A Scalable Front-End Architecture for Fast Instruction Delivery
In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance necessary to meet ...
Glenn Reinman, Todd M. Austin, Brad Calder
IPPS
2006
IEEE
14 years 1 months ago
The robot software communications architecture (RSCA): embedded middleware for networked service robots
In this paper, we present a robot middleware technology named Robot Software Communications Architecture (RSCA) for its use in networked home service robots. The RSCA provides a s...
Seongsoo Hong, Jaesoo Lee, Hyeonsang Eom, Gwangil ...