Sciweavers

1095 search results - page 70 / 219
» Measuring the Performance of Parallel Message-Based Process ...
Sort
View
HPCS
2002
IEEE
14 years 25 days ago
CoStore: A Reliable and Highly Available Storage System Using Clusters
The CoStore cluster architecture has been proposed to construct a reliable and highly available storage system. A prototype CoStore has been implemented and its performance has be...
Yong Chen, Lionel M. Ni, Cheng-Zhong Xu, Mingyao Y...
VLSISP
2008
132views more  VLSISP 2008»
13 years 7 months ago
Serial and Parallel FPGA-based Variable Block Size Motion Estimation Processors
H.264/AVC is the latest video coding standard adopting variable block size motion estimation (VBS-ME), quarter-pixel accuracy, motion vector prediction and multi-reference frames f...
Brian M. H. Li, Philip Heng Wai Leong
IEEEPACT
2008
IEEE
14 years 2 months ago
The PARSEC benchmark suite: characterization and architectural implications
This paper presents and characterizes the Princeton Application Repository for Shared-Memory Computers (PARSEC), a benchmark suite for studies of Chip-Multiprocessors (CMPs). Prev...
Christian Bienia, Sanjeev Kumar, Jaswinder Pal Sin...
DAC
2002
ACM
14 years 8 months ago
An energy saving strategy based on adaptive loop parallelization
In this paper, we evaluate an adaptive loop parallelization strategy (i.e., a strategy that allows each loop nest to execute using different number of processors if doing so is be...
Ismail Kadayif, Mahmut T. Kandemir, Mustafa Karak&...
CORR
2010
Springer
159views Education» more  CORR 2010»
13 years 7 months ago
A Novel VLSI Architecture of Fixed-complexity Sphere Decoder
Fixed-complexity sphere decoder (FSD) is a recently proposed technique for multiple-input multiple-output (MIMO) detection. It has several outstanding features such as constant thr...
Bin Wu, Guido Masera