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ICASSP
2010
IEEE
13 years 5 months ago
Bandwidth-intensive FPGA architecture for multi-dimensional DFT
Multi-dimensional (MD) Discrete Fourier Transform (DFT) is a key kernel algorithm in many signal processing algorithms, including radar data processing and medical imaging. Althou...
Chi-Li Yu, Chaitali Chakrabarti, Sungho Park, Vija...
EUROSYS
2007
ACM
13 years 9 months ago
Enabling scalability and performance in a large scale CMP environment
Hardware trends suggest that large-scale CMP architectures, with tens to hundreds of processing cores on a single piece of silicon, are iminent within the next decade. While exist...
Bratin Saha, Ali-Reza Adl-Tabatabai, Anwar M. Ghul...
AIPR
2008
IEEE
13 years 10 months ago
Low-cost, high-speed computer vision using NVIDIA's CUDA architecture
In this paper, we introduce real time image processing techniques using modern programmable Graphic Processing Units (GPU). GPUs are SIMD (Single Instruction, Multiple Data) device...
Seung In Park, Sean P. Ponce, Jing Huang, Yong Cao...
FPL
2004
Springer
110views Hardware» more  FPL 2004»
14 years 1 months ago
Versatile Imaging Architecture Based on a System on Chip
Abstract. In this paper, a novel architecture dedicated to image processing is presented. The most original aspect of the approach is the use of a System On Chip implemented in a F...
Pierre Chalimbaud, François Berry
FCCM
2006
IEEE
106views VLSI» more  FCCM 2006»
14 years 2 months ago
Scalable Hardware Architecture for Real-Time Dynamic Programming Applications
Abstract— This paper introduces a novel architecture for performing the core computations required by dynamic programming (DP) techniques. The latter pertain to a vast range of a...
Brad Matthews, Itamar Elhanany