4880 search results - page 847 / 976 » Mechanism Design by Creditability |
IEEEPACT
2006
IEEE
14 years 3 months ago
2006
IEEE
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
IPCCC
2006
IEEE
14 years 3 months ago
2006
IEEE
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
ISCAS
2006
IEEE
14 years 3 months ago
2006
IEEE
Abstract—We present a silicon neuron with a dynamic, active leak that enables precise spike-timing with respect to a time-varying input signal. Our neuron models the mammalian bu...
CASES
2006
ACM
14 years 3 months ago
2006
ACM
With advances in process technology, soft errors (SE) are becoming an increasingly critical design concern. Due to their large area and high density, caches are worst hit by soft ...
DAC
2006
ACM
14 years 3 months ago
2006
ACM
duce system weight and volume, increase operating lifetime, The recent explosion in capability of embedded and portable decrease maintenance costs, and open new frontiers for inele...