206 search results - page 6 / 42 » Mechanisms for store-wait-free multiprocessors |
NOCS
2008
IEEE
14 years 1 months ago
2008
IEEE
This paper introduces a cost-effective technique to deal with CMP coherence protocol requirements from the interconnection network point of view. A mechanism is presented to avoid...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
Functional, instruction-based self-testing of microprocessors has recently emerged as an effective alternative or supplement to other testing approaches, and is progressively adop...
PDPTA
2000
13 years 8 months ago
2000
This paper deals with multiprocessor systems required to provide both high performance and good figures of dependability attributes. Fault tolerance is pursued through a proper co...
PACT
2007
Springer
14 years 1 months ago
2007
Springer
Abstract. It has been already verified that hardware-supported finegrain synchronization provides a significant performance improvement over coarse-grained synchronization mecha...
IEEEPACT
2009
IEEE
13 years 4 months ago
2009
IEEE
Resource sharing can cause unfair and unpredictable performance of concurrently executing applications in Chip-Multiprocessors (CMP). The shared last-level cache is one of the mos...