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ISCA
2011
IEEE
324views Hardware» more  ISCA 2011»
13 years 2 months ago
Prefetch-aware shared resource management for multi-core systems
Chip multiprocessors (CMPs) share a large portion of the memory subsystem among multiple cores. Recent proposals have addressed high-performance and fair management of these share...
Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N....
ISPAN
2008
IEEE
14 years 5 months ago
An Expedite State Dissemination Mechanism for MMOGs
Massively Multiuser Online Game, i.e. MMOG, is an active research especially to integrate players to perform routing task with the intention of keeping the game deployment cost to...
Dewan Tanvir Ahmed, Shervin Shirmohammadi
CDC
2009
IEEE
132views Control Systems» more  CDC 2009»
14 years 3 months ago
A mechanism design approach to the stabilization of networked dynamical systems
— In this paper we study the problem of stabilizing a networked control system (NCS) composed of N linear dynamical subplants and an equal number of controllers acting over a sha...
Luca Galbusera, Nicola Gatti, Carlo Romani
CATA
2004
14 years 11 days ago
The Instruction Execution Mechanism for Responsive Multithreaded Processor
This paper describes the instruction execution mechanism of Responsive Multithreaded (RMT) Processor for distributed real-time processing. The execution order of each thread is co...
Tstomu Itou, Nobuyuki Yamasaki
TC
1998
13 years 10 months ago
Performance Evaluation and Cost Analysis of Cache Protocol Extensions for Shared-Memory Multiprocessors
—We evaluate three extensions to directory-based cache coherence protocols in shared-memory multiprocessors. These extensions are aimed at reducing the penalties associated with ...
Fredrik Dahlgren, Michel Dubois, Per Stenströ...