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GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
14 years 4 months ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
ISLPED
2005
ACM
100views Hardware» more  ISLPED 2005»
14 years 4 months ago
A tunable bus encoder for off-chip data buses
Off-Chip buses constitute a significant portion of the total system power in embedded systems. Past research has focused on encoding contiguous bit positions in data values to red...
Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Wa...
MM
2005
ACM
157views Multimedia» more  MM 2005»
14 years 4 months ago
Chameleon: application level power management with performance isolation
In this paper, we present Chameleon—an application-level power management approach for reducing energy consumption in mobile processors. Our approach exports the entire responsi...
Xiaotao Liu, Prashant J. Shenoy, Mark D. Corner
SENSYS
2005
ACM
14 years 4 months ago
Sympathy for the sensor network debugger
Being embedded in the physical world, sensor networks present a wide range of bugs and misbehavior qualitatively different from those in most distributed systems. Unfortunately, d...
Nithya Ramanathan, Kevin K. Chang, Rahul Kapur, Le...
SCOPES
2005
Springer
14 years 4 months ago
Software Synthesis from the Dataflow Interchange Format
Specification, validation, and synthesis are important aspects of embedded systems design. The use of dataflow-based design environments for these purposes is becoming increasingl...
Chia-Jui Hsu, Shuvra S. Bhattacharyya
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