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CASES
2007
ACM
14 years 1 months ago
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters....
Rahul Nagpal, Arvind Madan, Bharadwaj Amrutur, Y. ...
JFP
2000
163views more  JFP 2000»
13 years 9 months ago
Automatic useless-code elimination for HOT functional programs
In this paper we present two type inference systems for detecting useless-code in higher-order typed functional programs. Type inference can be performed in an efficient and compl...
Ferruccio Damiani, Paola Giannini
SENSYS
2009
ACM
14 years 4 months ago
Darjeeling, a feature-rich VM for the resource poor
The programming and retasking of sensor nodes could benefit greatly from the use of a virtual machine (VM) since byte code is compact, can be loaded on demand, and interpreted on...
Niels Brouwers, Koen Langendoen, Peter Corke
ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
13 years 11 months ago
Variability-driven module selection with joint design time optimization and post-silicon tuning
Abstract-- Increasing delay and power variation are significant challenges to the designers as technology scales to the deep sub-micron (DSM) regime. Traditional module selection t...
Feng Wang 0004, Xiaoxia Wu, Yuan Xie
CAV
2009
Springer
206views Hardware» more  CAV 2009»
14 years 10 months ago
D-Finder: A Tool for Compositional Deadlock Detection and Verification
D-Finder tool implements a compositional method for the verification of component-based systems described in BIP language encompassing multi-party interaction. For deadlock detecti...
Saddek Bensalem, Marius Bozga, Thanh-Hung Nguyen, ...