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DATE
2002
IEEE
105views Hardware» more  DATE 2002»
14 years 27 days ago
Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis
Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a giv...
Chunhong Chen, Majid Sarrafzadeh
LCTRTS
2004
Springer
14 years 1 months ago
Dynamic voltage scaling for real-time multi-task scheduling using buffers
This paper proposes energy efficient real-time multi-task scheduling (EDF and RM) algorithms by using buffers. The buffering technique overcomes a drawback of previous approaches ...
Chaeseok Im, Soonhoi Ha
ICCAD
1994
IEEE
137views Hardware» more  ICCAD 1994»
14 years 2 days ago
Dynamic scheduling and synchronization synthesis of concurrent digital systems under system-level constraints
We present in this paper a novel control synthesis technique for system-level specifications that are better described as a set of concurrent synchronous descriptions, their synch...
Claudionor José Nunes Coelho Jr., Giovanni ...
RTAS
2000
IEEE
14 years 10 days ago
Voltage-Clock-Scaling Adaptive Scheduling Techniques for Low Power in Hard Real-Time Systems
—Many embedded systems operate under severe power and energy constraints. Voltage clock scaling is one mechanism by which energy consumption may be reduced: It is based on the fa...
C. Mani Krishna, Yann-Hang Lee
ASPDAC
2008
ACM
154views Hardware» more  ASPDAC 2008»
13 years 10 months ago
Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures
Abstract-- We address performance maximization of independent task sets under energy constraint on chip multi-processor (CMP) architectures that support multiple voltage/frequency ...
Sushu Zhang, Karam S. Chatha