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ICCAD
2003
IEEE
152views Hardware» more  ICCAD 2003»
14 years 4 months ago
Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
Nam Sung Kim, David Blaauw, Trevor N. Mudge
DSN
2005
IEEE
14 years 1 months ago
Checking Array Bound Violation Using Segmentation Hardware
The ability to check memory references against their associated array/buffer bounds helps programmers to detect programming errors involving address overruns early on and thus avo...
Lap-Chung Lam, Tzi-cker Chiueh
ASPLOS
2010
ACM
13 years 11 months ago
Butterfly analysis: adapting dataflow analysis to dynamic parallel monitoring
Online program monitoring is an effective technique for detecting bugs and security attacks in running applications. Extending these tools to monitor parallel programs is challeng...
Michelle L. Goodstein, Evangelos Vlachos, Shimin C...
CCS
2009
ACM
13 years 11 months ago
Filter-resistant code injection on ARM
Code injections attacks are one of the most powerful and important classes of attacks on software. In such attacks, the attacker sends malicious input to a software application, w...
Yves Younan, Pieter Philippaerts, Frank Piessens, ...
SPE
1998
129views more  SPE 1998»
13 years 7 months ago
Timing Trials, or the Trials of Timing: Experiments with Scripting and User-Interface Languages
This paper describes some basic experiments to see how fast various popular scripting and user-interface languages run on a spectrum of representative tasks. We found enormous var...
Brian W. Kernighan, Christopher J. Van Wyk