98 search results - page 3 / 20 » Memory Access Scheduling Schemes for Systems with Multi-Core... |
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
Modern DRAM systems rely on memory controllers that employ out-of-order scheduling to maximize row access locality and bank-level parallelism, which in turn maximizes DRAM bandwid...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Transistor leakage is poised to become the dominant source of power dissipation in digital systems, and reconfigurable devices are not immune to this problem. Modern FPGAs already...
TVLSI
2002
13 years 7 months ago
2002
We propose a technique for reducing the energy spent in the memory-processor interface of an embedded system during the execution of firmware code. The method is based on the idea ...
ICS
2000
Tsinghua U.
13 years 11 months ago
2000
Tsinghua U.
Memory system bottlenecks limit performance for many applications, and computations with strided access patterns are among the hardest hit. The streams used in such applications h...
HOTOS
2009
IEEE
13 years 11 months ago
2009
IEEE
High performance on multicore processors requires that schedulers be reinvented. Traditional schedulers focus on keeping execution units busy by assigning each core a thread to ru...