117 search results - page 15 / 24 » Memory Access Schemes for Configurable Processors |
TC
2008
13 years 7 months ago
2008
To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB). However, this curre...
CF
2005
ACM
13 years 9 months ago
2005
ACM
Power consumption within the memory hierarchy grows in importance as on-chip data caches occupy increasingly greater die area. Among dynamic power conservation schemes, horizontal...
HIPEAC
2005
Springer
14 years 1 months ago
2005
Springer
Abstract. Power efficiency has become a key design trade-off in embedded system designs. For system-on-a-chip embedded systems, an external bus interconnects embedded processor co...
CF
2006
ACM
14 years 1 months ago
2006
ACM
The discrete wavelet transform (DWT) is used in several image and video compression standards, in particular JPEG2000. A 2D DWT consists of horizontal filtering along the rows fo...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...