117 search results - page 8 / 24 » Memory Access Schemes for Configurable Processors |
EUROPAR
1995
Springer
13 years 11 months ago
1995
Springer
The growing disparity between processor and memory speeds has caused memory bandwidth to become the performance bottleneck for many applications. In particular, this performance ga...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
One of the main challenges of modern processor design is the implementation of a scalable and efficient mechanism to detect memory access order violations as a result of out-of-o...
CASES
2007
ACM
13 years 11 months ago
2007
ACM
Recently dual-port SDRAM (DPSDRAM) architecture tailored for dual-processor based mobile embedded systems has been announced where a single memory chip plays the role of the local...
HPCA
1999
IEEE
14 years 1 hour ago
1999
IEEE
Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through...
ICPP
2008
IEEE
14 years 2 months ago
2008
IEEE
This paper presents a two-part study on managing distributed NUCA (Non-Uniform Cache Architecture) L2 caches in a future manycore processor to obtain high singlethread program per...