167 search results - page 18 / 34 » Memory Arbitration and Cache Management in Stream-Based Syst... |
ISCA
2000
IEEE
14 years 5 days ago
2000
IEEE
As DRAM access latencies approach a thousand instructionexecution times and on-chip caches grow to multiple megabytes, it is not clear that conventional cache structures continue ...
SIGMETRICS
1996
ACM
13 years 12 months ago
1996
ACM
This paper describes Embra, a simulator for the processors, caches, and memory systems of uniprocessors and cache-coherent multiprocessors. When running as part of the SimOS simul...
TC
2008
13 years 7 months ago
2008
To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB). However, this curre...
USENIX
1994
13 years 9 months ago
1994
We considerhowtoimprovetheperformanceof le cachingbyallowinguser-levelcontrolover lecache replacementdecisions. Weusetwo-levelcachemanagement: the kernel allocates physical pages ...
ASPLOS
2008
ACM
13 years 9 months ago
2008
ACM
Nested paging is a hardware solution for alleviating the software memory management overhead imposed by system virtualization. Nested paging complements existing page walk hardwar...