A fully associative software-managed cache design

As DRAM access latencies approach a thousand instructionexecution times and on-chip caches grow to multiple megabytes, it is not clear that conventional cache structures continue to be appropriate. Two key featuresfull associativity and software managementhave been used successfully in the virtual-memory domain to cope with disk access latencies. Future systems will need to employ similar techniques to deal with DRAM latencies. This paper presents a practical, fully associative, software-managed secondary cache system that provides performance competitive with or superior to traditional caches without OS or application involvement. We see this structure as the first step toward OS- and application-aware management of large on-chip caches. This paper has two primary contributions: a practical design for a fully associative memory structure, the indirect index cache (IIC), and a novel replacement algorithm, generational replacement, that is specifically designed to work with the I...

• Type: Conference
• Year: 2000
• Where: ISCA
• Authors: Erik G. Hallnor, Steven K. Reinhardt
• Keywords: Cache, Conventional Cache, DRAM Latencies, Hardware, ISCA 2000