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» Memory Aware High-Level Synthesis for Embedded Systems
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ICAC
2006
IEEE
14 years 1 months ago
QMON: QoS- and Utility-Aware Monitoring in Enterprise Systems
Abstract— The scale, reliability, and cost requirements of enterprise data centers require automation of center management. Examples include provisioning, scheduling, capacity pl...
Sandip Agarwala, Yuan Chen, Dejan S. Milojicic, Ka...
SAMOS
2010
Springer
13 years 5 months ago
Power aware heterogeneous MPSoC with dynamic task scheduling and increased data locality for multiple applications
A new heterogeneous multiprocessor system with dynamic memory and power management for improved performance and power consumption is presented. Increased data locality is automatic...
Oliver Arnold, Gerhard Fettweis
LCTRTS
2004
Springer
14 years 26 days ago
Flattening statecharts without explosions
We present a polynomial upper bound for flattening of UML statecharts. An efficient flattening technique is derived and implemented in SCOPE—a code generator targeting constra...
Andrzej Wasowski
IESS
2007
Springer
165views Hardware» more  IESS 2007»
14 years 1 months ago
Data Reuse Driven Memory and Network-On-Chip Co-Synthesis
NoCs present a possible communication infrastructure solution to deal with increased design complexity and shrinking time-to-market. The communication infrastructure is a signific...
Ilya Issenin, Nikil Dutt
CASES
2008
ACM
13 years 9 months ago
Optimus: efficient realization of streaming applications on FPGAs
In this paper, we introduce Optimus: an optimizing synthesis compiler for streaming applications. Optimus compiles programs written in a high level streaming language to either so...
Amir Hormati, Manjunath Kudlur, Scott A. Mahlke, D...