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» Memory Aware High-Level Synthesis for Embedded Systems
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DAC
2000
ACM
14 years 8 months ago
Memory aware compilation through accurate timing extraction
Memory delays represent a major bottleneck in embedded systems performance. Newer memory modules exhibiting efficient access modes (e.g., page-, burst-mode) partly alleviate this ...
Peter Grun, Nikil D. Dutt, Alexandru Nicolau
EIT
2008
IEEE
14 years 1 months ago
Architectural support for securing application data in embedded systems
—The rapid growth and pervasive use of embedded systems makes it easier for an adversary to gain physical access to these devices to launch attacks and reverse engineer of the sy...
Olga Gelbart, Eugen Leontie, Bhagirath Narahari, R...
RTCSA
2008
IEEE
14 years 1 months ago
Power-Aware Data Buffer Cache Management in Real-Time Embedded Databases
The demand for real-time data services in embedded systems is increasing. In these new computing platforms, using traditional buffer management schemes, whose goal is to minimize ...
Woochul Kang, Sang Hyuk Son, John A. Stankovic
CODES
2007
IEEE
14 years 1 months ago
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC
Heterogeneous multiprocessors are emerging as the dominant implementation approach to embedded multiprocessor systems. In addition to having processing elements suited to the targ...
Brett H. Meyer, Donald E. Thomas
ISSS
2002
IEEE
151views Hardware» more  ISSS 2002»
14 years 12 days ago
Tuning of Loop Cache Architectures to Programs in Embedded System Design
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
Frank Vahid, Susan Cotterell