236 search results - page 21 / 48 » Memory Bank Predictors |
ICS
1998
Tsinghua U.
14 years 1 days ago
1998
Tsinghua U.
In order to achieve high performance, contemporary microprocessors must effectively process the four major instruction types: ALU, branch, load, and store instructions. This paper...
CODES
2000
IEEE
14 years 7 days ago
2000
IEEE
Memory interleaving is a cost-efficient approach to increase bandwidth. Improving data access locality and reducing memory access conflicts are two important aspects to achieve hi...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
ISCAPDCS
2004
13 years 9 months ago
2004
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
Abstract— In this paper, we describe the design and implementation of the primary memory system of the TRIPS processor. To match the aggressive execution bandwidth and support hi...