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HPCA
2009
IEEE
14 years 8 months ago
PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches
As the last-level on-chip caches in chip-multiprocessors increase in size, the physical locality of on-chip data becomes important for delivering high performance. The non-uniform...
Mainak Chaudhuri
RTAS
2010
IEEE
13 years 6 months ago
DARTS: Techniques and Tools for Predictably Fast Memory Using Integrated Data Allocation and Real-Time Task Scheduling
—Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which im...
Sangyeol Kang, Alexander G. Dean
IPPS
2006
IEEE
14 years 1 months ago
Quantifying and reducing the effects of wrong-path memory references in cache-coherent multiprocessor systems
High-performance multiprocessor systems built around out-of-order processors with aggressive branch predictors execute many memory references that turn out to be on a mispredicted...
Resit Sendag, Ayse Yilmazer, Joshua J. Yi, Augustu...
INFOCOM
2005
IEEE
14 years 1 months ago
Predicting Internet end-to-end delay: a multiple-model approach
This paper presents a novel approach to predict the Internet end-to-end delay using multiple-model (MM) methods. The basic idea of the MM method is to assume the system dynamics c...
Ming Yang, Jifeng Ru, X. Rong Li, Huimin Chen, Anw...
CANDC
2006
ACM
13 years 7 months ago
Prediction of protein subcellular location using hydrophobic patterns of amino acid sequence
The function of eukaryotic protein is closely correlated with its subcellular location. The number of newly found protein sequences entering into data banks is rapidly increasing ...
Tongliang Zhang, Yongsheng Ding, Kuo-Chen Chou