236 search results - page 37 / 48 » Memory Bank Predictors |
CAL
2010
13 years 5 months ago
2010
This paper describes dynamic pressure-aware associative placement (DPAP), a novel distributed cache management scheme for large-scale chip multiprocessors. Our work is motivated by...
EJC
2010
13 years 2 months ago
2010
As a computational model of natural language communication, Database Semantics1 (DBS) includes a hearer mode and a speaker mode. For the content to be mapped into language expressi...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
The load/store queue (LSQ) is one of the most complex parts of contemporary processors. Its latency is critical for the processor performance and it is usually one of the processo...
IPPS
2010
IEEE
13 years 5 months ago
2010
IEEE
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
HPCA
2003
IEEE
14 years 8 months ago
2003
IEEE
Although caches for decades have been the backbone of the memory system, the speed gap between CPU and main memory suggests their augmentation with prefetching mechanisms. Recentl...