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» Memory Dependence Prediction Using Store Sets
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ISCA
2005
IEEE
144views Hardware» more  ISCA 2005»
14 years 21 days ago
Scalable Load and Store Processing in Latency Tolerant Processors
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
Amit Gandhi, Haitham Akkary, Ravi Rajwar, Srikanth...
ICDE
2010
IEEE
288views Database» more  ICDE 2010»
14 years 6 months ago
Fast In-Memory XPath Search using Compressed Indexes
A large fraction of an XML document typically consists of text data. The XPath query language allows text search via the equal, contains, and starts-with predicates. Such predicate...
Diego Arroyuelo, Francisco Claude, Sebastian Manet...
MICRO
2003
IEEE
108views Hardware» more  MICRO 2003»
14 years 11 days ago
Reducing Design Complexity of the Load/Store Queue
With faster CPU clocks and wider pipelines, all relevant microarchitecture components should scale accordingly. There have been many proposals for scaling the issue queue, registe...
Il Park, Chong-liang Ooi, T. N. Vijaykumar
CAV
2008
Springer
96views Hardware» more  CAV 2008»
13 years 9 months ago
Implied Set Closure and Its Application to Memory Consistency Verification
Hangal et. al. [3] have developed a procedure to check if an instance of the execution of a shared memory multiprocessor program, is consistent with the Total Store Order (TSO) mem...
Surender Baswana, Shashank K. Mehta, Vishal Powar
IJCNN
2007
IEEE
14 years 1 months ago
A Cell Assembly Model of Sequential Memory
—Perception, prediction and generation of sequences is a fundamental aspect of human behavior and depends on the ability to detect serial order. This paper presents a plausible m...
Hina Ghalib, Christian R. Huyck