60 search results - page 10 / 12 » Memory Estimation for High Level Synthesis |
VLSID
2003
IEEE
14 years 8 months ago
2003
IEEE
Design of efficient System-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardwa...
DCC
2003
IEEE
14 years 7 months ago
2003
IEEE
The Prediction by Partial Matching (PPM) algorithm uses a cumulative frequency count of input symbols in different contexts to estimate their probability distribution. Excellent c...
TCAD
2008
13 years 7 months ago
2008
Abstract--The fabrication of crossbar memories with sublithographic features is expected to be feasible within several emerging technologies; in all of them, the nanowire (NW) deco...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
— Caches, block memories, predictors, state tables, and other forms of on-chip memory are continuing to consume a greater portion of processor designs with each passing year. Mak...
RTAS
2010
IEEE
13 years 6 months ago
2010
IEEE
—Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which im...