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» Memory Exploration for Low Power, Embedded Systems
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DATE
2005
IEEE
143views Hardware» more  DATE 2005»
14 years 1 months ago
Q-DPM: An Efficient Model-Free Dynamic Power Management Technique
When applying Dynamic Power Management (DPM) technique to pervasively deployed embedded systems, the technique needs to be very efficient so that it is feasible to implement the t...
Min Li, Xiaobo Wu, Richard Yao, Xiaolang Yan
HIPEAC
2005
Springer
14 years 1 months ago
Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems
Abstract. Power efficiency has become a key design trade-off in embedded system designs. For system-on-a-chip embedded systems, an external bus interconnects embedded processor co...
Ke Ning, David R. Kaeli
ESORICS
2009
Springer
14 years 8 months ago
Cumulative Attestation Kernels for Embedded Systems
1 There are increasing deployments of networked embedded systems and rising threats of malware intrusions on such systems. To mitigate this threat, it is desirable to enable common...
Michael LeMay, Carl A. Gunter
DAC
2002
ACM
14 years 8 months ago
A fast on-chip profiler memory
Profiling an application executing on a microprocessor is part of the solution to numerous software and hardware optimization and design automation problems. Most current profilin...
Roman L. Lysecky, Susan Cotterell, Frank Vahid
MICRO
1997
IEEE
139views Hardware» more  MICRO 1997»
13 years 12 months ago
The Filter Cache: An Energy Efficient Memory Structure
Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occu...
Johnson Kin, Munish Gupta, William H. Mangione-Smi...