102 search results - page 14 / 21 » Memory Interfacing and Instruction Specification for Reconfi... |
SIGMOD
2007
ACM
14 years 8 months ago
2007
ACM
We propose to demonstrate EaseDB, the first cache-oblivious query processor for in-memory relational query processing. The cacheoblivious notion from the theory community refers t...
ICCAD
1994
IEEE
14 years 21 days ago
1994
IEEE
Application Specific Instruction-Set Processors (ASIPs) offer designers the ability for high-speed data and control processing with the added flexibility needed for late design sp...
ASAP
2008
IEEE
13 years 10 months ago
2008
IEEE
This paper presents a multiprocessor system on FPGA that adopts Direct Memory Access (DMA) mechanisms to move data between the external memory and the local memory of each process...
VLSID
2005
IEEE
14 years 9 months ago
2005
IEEE
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
CANPC
1999
Springer
14 years 25 days ago
1999
Springer
Streamlining communication is key to achieving good performance in shared-memory parallel programs. While full hardware support for cache coherence generally offers the best perfo...