102 search results - page 8 / 21 » Memory Interfacing and Instruction Specification for Reconfi... |
127
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IPPS
2007
IEEE
15 years 10 months ago
2007
IEEE
The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconfiguration, also known as dynamic partial reconfiguration (DPR). Taking this concept one st...
112
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DAC
1996
ACM
15 years 8 months ago
1996
ACM
The advent of parallel executing Address Calculation Units (ACUs) in Digital Signal Processor (DSP) and Application Specific InstructionSet Processor (ASIP) architectures has made...
110
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ISCA
1997
IEEE
15 years 8 months ago
1997
IEEE
Prefetching is one approach to reducing the latency of memory operations in modern computer systems. In this paper, we describe the Markov prefetcher. This prefetcher acts as an i...
129
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VLSID
2001
IEEE
16 years 4 months ago
2001
IEEE
Networking hardware manufacturers face the dual demands of supporting ever increasing bandwidth requirements, while also delivering new features, such as the ability to implement ...
156
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EH
2004
IEEE
15 years 7 months ago
2004
IEEE
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...