34 search results - page 6 / 7 » Memory Model = Instruction Reordering Store Atomicity |
ICCD
2001
IEEE
14 years 4 months ago
2001
IEEE
The general-purpose precise interrupt mechanism, which has long been used to handle exceptional conditions that occur infrequently, is now being used increasingly often to handle ...
POPL
2009
ACM
14 years 8 months ago
2009
ACM
Speed improvements in today's processors have largely been delivered in the form of multiple cores, increasing the importance of ions that ease parallel programming. Software...
SPAA
2010
ACM
14 years 8 days ago
2010
ACM
Transactional memory (TM) has shown potential to simplify the task of writing concurrent programs. Inspired by classical work on databases, formal definitions of the semantics of...
CF
2006
ACM
13 years 11 months ago
2006
ACM
This paper presents our experience mapping OpenMP parallel programming model to the IBM Cyclops-64 (C64) architecture. The C64 employs a many-core-on-a-chip design that integrates...
ASPLOS
2011
ACM
12 years 11 months ago
2011
ACM
Providing deterministic execution significantly simplifies the debugging, testing, replication, and deployment of multithreaded programs. Recent work has developed deterministic...