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CASES
2005
ACM
13 years 9 months ago
Compilation techniques for energy reduction in horizontally partitioned cache architectures
Horizontally partitioned data caches are a popular architectural feature in which the processor maintains two or more data caches at the same level of hierarchy. Horizontally part...
Aviral Shrivastava, Ilya Issenin, Nikil Dutt
ISCAPDCS
2003
13 years 8 months ago
Utilization of Separate Caches to Eliminate Cache Pollution Caused by Memory Management Functions
Data intensive service functions such as memory allocation/de-allocation, data prefetching, and data relocation can pollute processor cache in conventional systems since the same ...
Mehran Rezaei, Krishna M. Kavi
TVLSI
2008
150views more  TVLSI 2008»
13 years 6 months ago
Data Memory Subsystem Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance o...
M. Bennaser, Yao Guo, Csaba Andras Moritz
ISCA
2005
IEEE
99views Hardware» more  ISCA 2005»
14 years 29 days ago
Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking
To maintain coherence in conventional shared-memory multiprocessor systems, processors first check other processors’ caches before obtaining data from memory. This coherence che...
Jason F. Cantin, Mikko H. Lipasti, James E. Smith
LCTRTS
2005
Springer
14 years 26 days ago
Cache aware optimization of stream programs
Effective use of the memory hierarchy is critical for achieving high performance on embedded systems. We focus on the class of streaming applications, which is increasingly preval...
Janis Sermulins, William Thies, Rodric M. Rabbah, ...