276 search results - page 45 / 56 » Memory Organization for Improved Data Cache Performance in E... |
CLUSTER
2006
IEEE
14 years 2 months ago
2006
IEEE
As new processor and memory architectures advance, clusters start to be built from larger SMP systems, which makes MPI intra-node communication a critical issue in high performanc...
ICS
2003
Tsinghua U.
14 years 1 months ago
2003
Tsinghua U.
Cache behavior modeling is an important part of modern optimizing compilers. In this paper we present a method to estimate the number of cache misses, at compile time, using a mac...
IEEEPACT
2009
IEEE
13 years 6 months ago
2009
IEEE
As the gap between processor and memory continues to grow, memory performance becomes a key performance bottleneck for many applications. Compilers therefore increasingly seek to m...
HPCA
2011
IEEE
12 years 12 months ago
2011
IEEE
Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization...
EMSOFT
2005
Springer
14 years 2 months ago
2005
Springer
With the scaling of technology, transient errors caused by external particle strikes have become a critical challenge for microprocessor design. As embedded processors are widely ...