283 search results - page 53 / 57 » Memory Resource Management for Real-Time Systems |
IISWC
2006
IEEE
14 years 3 months ago
2006
IEEE
— As CMPs are emerging as the dominant architecture for a wide range of platforms (from embedded systems and game consoles, to PCs, and to servers) the need to manage on-chip res...
HIPEAC
2009
Springer
14 years 4 months ago
2009
Springer
Developing streaming applications on heterogenous multi-processor architectures like the Cell is difficult. Currently, application developers need to know about hardware details t...
AAAIDEA
2005
IEEE
14 years 3 months ago
2005
IEEE
—Differentiated Service (DiffServ) in combination with Multi-Protocol Label Switching (MPLS) is a promising technology in converting the best-effort Internet into a QoS-capable n...
CGO
2005
IEEE
14 years 3 months ago
2005
IEEE
To improve performance and reduce power, processor designers employ advances that shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates. Howev...
HPCA
2008
IEEE
14 years 10 months ago
2008
IEEE
Power-Efficient DRAM Speculation (PEDS) is a power optimization targeted at broadcast-based sharedmemory multiprocessor systems that speculatively access DRAM in parallel with the...