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» Memory System Connectivity Exploration
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117
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TLCA
2005
Springer
15 years 8 months ago
L3: A Linear Language with Locations
We explore foundational typing support for strong updates — updating a memory cell to hold values of unrelated types at different points in time. We present a simple, but expres...
Greg Morrisett, Amal J. Ahmed, Matthew Fluet
115
Voted
DATE
2003
IEEE
132views Hardware» more  DATE 2003»
15 years 8 months ago
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design
On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip co...
Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung C...
DATE
2002
IEEE
123views Hardware» more  DATE 2002»
15 years 7 months ago
False Path Elimination in Quasi-Static Scheduling
We have developed a technique to compute a Quasi Static Schedule of a concurrent specification for the software partition of an embedded system. Previous work did not take into a...
G. Arrigoni, L. Duchini, Claudio Passerone, Lucian...
ISCA
2002
IEEE
82views Hardware» more  ISCA 2002»
15 years 7 months ago
Increasing Processor Performance by Implementing Deeper Pipelines
One architectural method for increasing processor performance involves increasing the frequency by implementing deeper pipelines. This paper will explore the relationship between ...
Eric Sprangle, Doug Carmean
CAV
2000
Springer
97views Hardware» more  CAV 2000»
15 years 7 months ago
Detecting Errors Before Reaching Them
Abstract. Any formalmethodor tool is almostcertainlymoreoftenapplied in situationswheretheoutcomeis failure(acounterexample)rather than success (a correctness proof). We present a ...
Luca de Alfaro, Thomas A. Henzinger, Freddy Y. C. ...