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146
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FORMATS
2007
Springer
15 years 6 months ago
Partial Order Reduction for Verification of Real-Time Components
Abstract. We describe a partial order reduction technique for a realtime component model. Components are described as timed automata with data ports, which can be composed in stati...
John Håkansson, Paul Pettersson
DSD
2004
IEEE
129views Hardware» more  DSD 2004»
15 years 6 months ago
Functional Validation of Programmable Architectures
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
Prabhat Mishra, Nikil D. Dutt
126
Voted
KDD
1995
ACM
148views Data Mining» more  KDD 1995»
15 years 6 months ago
Learning Arbiter and Combiner Trees from Partitioned Data for Scaling Machine Learning
Knowledge discovery in databases has become an increasingly important research topic with the advent of wide area network computing. One of the crucial problems we study in this p...
Philip K. Chan, Salvatore J. Stolfo
123
Voted
ASAP
2006
IEEE
147views Hardware» more  ASAP 2006»
15 years 4 months ago
Reconfigurable Shuffle Network Design in LDPC Decoders
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
Jun Tang, Tejas Bhatt, Vishwas Sundaramurthy
114
Voted
EMSOFT
2008
Springer
15 years 4 months ago
Energy efficient streaming applications with guaranteed throughput on MPSoCs
In this paper we present a design space exploration flow to achieve energy efficiency for streaming applications on MPSoCs while meeting the specified throughput constraints. The ...
Jun Zhu, Ingo Sander, Axel Jantsch