3202 search results - page 30 / 641 » Memory access scheduling |
ISLPED
2006
ACM
14 years 4 months ago
2006
ACM
Buffering more in-flight instructions in an out-of-order microprocessor is a straightforward and effective method to help tolerate the long latencies generally associated with ...
ASPDAC
2006
ACM
14 years 4 months ago
2006
ACM
Abstract—H.264/AVC is the latest video coding standard. It significantly outperforms the previous video coding standards, but the extraordinary huge computation complexity and m...
ISSS
1999
IEEE
14 years 2 months ago
1999
IEEE
Partition Scheduling with Prefetching (PSP) is a memory latency hiding technique which combines the loop pipelining technique with data prefetching. In PSP, the iteration space is...
CLOUDCOM
2009
Springer
14 years 2 months ago
2009
Springer
Workflows are modeled as hierarchically structured directed acyclic graphs in which vertices represent computational tasks, referred to as requests, and edges represent precedent c...
ISCA
2011
IEEE
13 years 1 months ago
2011
IEEE
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...