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ISCA
2000
IEEE
121views Hardware» more  ISCA 2000»
14 years 21 days ago
Selective, accurate, and timely self-invalidation using last-touch prediction
Communication in cache-coherent distributed shared memory (DSM) often requires invalidating (or writing back) cached copies of a memory block, incurring high overheads. This paper...
An-Chow Lai, Babak Falsafi
ISCA
1997
IEEE
108views Hardware» more  ISCA 1997»
14 years 15 days ago
The SGI Origin: A ccNUMA Highly Scalable Server
The SGI Origin 2000 is a cache-coherent non-uniform memory access (ccNUMA) multiprocessor designed and manufactured by Silicon Graphics, Inc. The Origin system was designed from t...
James Laudon, Daniel Lenoski
CGO
2006
IEEE
14 years 1 days ago
Profiling over Adaptive Ranges
Modern computer systems are called on to deal with billions of events every second, whether they are instructions executed, memory locations accessed, or packets forwarded. This p...
Shashidhar Mysore, Banit Agrawal, Timothy Sherwood...
CASES
2001
ACM
13 years 12 months ago
Transparent data-memory organizations for digital signal processors
Today's digital signal processors (DSPs), unlike general-purpose processors, use a non-uniform addressing model in which the primary components of the memory system--the DRAM...
Sadagopan Srinivasan, Vinodh Cuppu, Bruce L. Jacob
ASPLOS
2008
ACM
13 years 10 months ago
Hardbound: architectural support for spatial safety of the C programming language
The C programming language is at least as well known for its absence of spatial memory safety guarantees (i.e., lack of bounds checking) as it is for its high performance. C'...
Joe Devietti, Colin Blundell, Milo M. K. Martin, S...