3202 search results - page 432 / 641 » Memory access scheduling |
ASPLOS
2010
ACM
14 years 3 months ago
2010
ACM
The behavior of a multithreaded program does not depend only on its inputs. Scheduling, memory reordering, timing, and low-level hardware effects all introduce nondeterminism in t...
PDCAT
2009
Springer
14 years 2 months ago
2009
Springer
Abstract—In this paper, a tool named CheCUDA is designed to checkpoint CUDA applications that use GPUs as accelerators. As existing checkpoint/restart implementations do not supp...
CF
2006
ACM
14 years 2 months ago
2006
ACM
Packet processing systems maintain high throughput despite relatively high memory latencies by exploiting the coarse-grained parallelism available between packets. In particular, ...
FPGA
2010
ACM
13 years 8 months ago
2010
ACM
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
ICDE
2000
IEEE
14 years 9 months ago
2000
IEEE
Push-based data delivery requires knowledge of user interests for making scheduling, bandwidthallocation, and routing decisions. Such information is maintained as user profiles. W...