3202 search results - page 441 / 641 » Memory access scheduling |
MICRO
2010
IEEE
13 years 6 months ago
2010
IEEE
Abstract-- We consider the problem of how to improve memory latency tolerance in massively multithreaded GPGPUs when the thread-level parallelism of an application is not sufficien...
TVCG
2010
13 years 2 months ago
2010
Abstract--One important bottleneck when visualizing large data sets is the data transfer between processor and memory. Cacheaware (CA) and cache-oblivious (CO) algorithms take into...
JOCN
2011
12 years 11 months ago
2011
■ Observers spontaneously segment larger activities into smaller events. For example, “washing a car” might be segmented into “scrubbing,” “rinsing,” and “drying...
ISLPED
2004
ACM
14 years 1 months ago
2004
ACM
While set-associative caches incur fewer misses than directmapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are p...
IWSOC
2003
IEEE
14 years 1 months ago
2003
IEEE
: - A filter cache is proposed at a higher level than the L1 (main) cache in the memory hierarchy and is much smaller. The typical size of filter cache is of the order of 512 Bytes...