3202 search results - page 45 / 641 » Memory access scheduling |
110
Voted
FOSAD
2009
Springer
15 years 6 months ago
2009
Springer
A program verifier is a tool that allows developers to prove that their code satisfies its specification for every possible input and every thread schedule. These lecture notes des...
145
Voted
ISCAPDCS
2001
15 years 4 months ago
2001
This paper presents the evaluation of a non-blocking, decoupled memory/execution, multithreaded architecture known as the Scheduled Dataflow (SDF). The major recent trend in digit...
114
Voted
JEC
2006
15 years 2 months ago
2006
Chip multi-processors (CMP) are rapidly emerging as an important design paradigm for both high performance and embedded processors. These machines provide an important performance...
124
Voted
HPCA
2007
IEEE
16 years 3 months ago
2007
IEEE
Memory bugs are a broad class of bugs that is becoming increasingly common with increasing software complexity, and many of these bugs are also security vulnerabilities. Unfortuna...
106
Voted
HPCA
1999
IEEE
15 years 7 months ago
1999
IEEE
Processor speeds are increasing rapidly, and memory speeds are not keeping up. Streaming computations (such as multi-media or scientific applications) are among those whose perfor...