3202 search results - page 4 / 641 » Memory access scheduling |
FPL
2007
Springer
14 years 1 months ago
2007
Springer
In this paper, we propose a first step towards a time predictable computer architecture for single-chip multiprocessing (CMP). CMP is the actual trend in server and desktop syste...
ICPP
1999
IEEE
13 years 12 months ago
1999
IEEE
Most of today's multiprocessors have a DistributedShared Memory (DSM) organization, which enables scalability while retaining the convenience of the shared-memory programming...
ISCA
1999
IEEE
13 years 12 months ago
1999
IEEE
State of the art microprocessors achieve high performance by executing multiple instructions per cycle. In an out-oforder engine, the instruction scheduler is responsible for disp...
ARCS
2004
Springer
14 years 1 months ago
2004
Springer
: We introduce the concept of an operating system for platforms that consist beside memory and peripheral devices of FPGAs as the only computational resource. Applications can be d...
ICASSP
2008
IEEE
14 years 2 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...