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ICS
1998
Tsinghua U.
14 years 8 days ago
Load Execution Latency Reduction
In order to achieve high performance, contemporary microprocessors must effectively process the four major instruction types: ALU, branch, load, and store instructions. This paper...
Bryan Black, Brian Mueller, Stephanie Postal, Ryan...
WETICE
1997
IEEE
14 years 7 days ago
Capturing Geometry Rationale for Collaborative Design
When an artifact is designed the typical output consists of documents describing the final result of a long series of deliberations and tradeoffs by the participants of collaborat...
Mark Klein
ASPDAC
2007
ACM
95views Hardware» more  ASPDAC 2007»
14 years 1 days ago
Low Power Techniques for Mobile Application SoCs Based on Integrated Platform "UniPhier"
In this Paper, we describe the various low power techniques for mobile application SoCs based on the integrated platform "UniPhier". To minimize SoC power dissipation, h...
Masaitsu Nakajima, Takao Yamamoto, Masayuki Yamasa...
GLOBECOM
2009
IEEE
13 years 12 months ago
Energy-Efficient Multi-Pipeline Architecture for Terabit Packet Classification
Energy efficiency has become a critical concern in designing high speed packet classification engines for next generation routers. Although TCAM-based solutions can provide high th...
Weirong Jiang, Viktor K. Prasanna
LCR
2000
Springer
129views System Software» more  LCR 2000»
13 years 11 months ago
Run-Time Support for Distributed Sharing in Typed Languages
We present a new run-time system for typed programming languages that supports object sharing in a distributed system. The key insight in this system is that the ability to distin...
Y. Charlie Hu, Weimin Yu, Alan L. Cox, Dan S. Wall...