60 search results - page 8 / 12 » Memory-constrained Block Processing for DSP Software Optimiz... |
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
- TOSHIBA has developed mobile multi-media engine SoC, we call as S1G, which can realize low power ISDB-T one-segment decode in 42mW for eight months short period of time. Since MP...
FCCM
1999
IEEE
13 years 11 months ago
1999
IEEE
Abstract We are developing an integrated algorithm analysis and mapping environment particularly tailored for signal processing applications on Adaptive Computing Systems ACS. Our ...
PARA
2004
Springer
14 years 25 days ago
2004
Springer
Cache optimizations typically include code transformations to increase the locality of memory accesses. An orthogonal approach is to enable for latency hiding by introducing prefet...
HPCA
2004
IEEE
14 years 7 months ago
2004
IEEE
This paper focuses on generating efficient software pipelined schedules for in-order machines, which we call Converged Trace Schedules. For a candidate loop, we form a string of t...
CODES
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper, we present a new architectural concept for network processors called FlexPath NP. The central idea behind FlexPath NP is to systematically map network processor (NP...