33 search results - page 5 / 7 » Meta-heuristics for Circuit Partitioning in Parallel Test Ge... |
DATE
2002
IEEE
14 years 19 days ago
2002
IEEE
System-on-chip (SOC) design methodology is becoming the trend in the IC industry. Integrating reusable cores from multiple sources is essential in SOC design, and different design...
MTDT
2003
IEEE
14 years 29 days ago
2003
IEEE
Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be ...
ASPDAC
2011
ACM
12 years 11 months ago
2011
ACM
3-D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. Since the device layers are processed in sequent...
ASPDAC
2004
ACM
13 years 11 months ago
2004
ACM
- Minimum area is one of the important objectives in technology mapping for lookup table-based FPGAs. It has been proven that the problem is NP-complete. This paper presents a poly...
DFT
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...