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» Methods for true power minimization
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DAC
2005
ACM
14 years 8 months ago
An effective power mode transition technique in MTCMOS circuits
- The large magnitude of supply/ground bounces, which arise from power mode transitions in power gating structures, may cause spurious transitions in a circuit. This can result in ...
Afshin Abdollahi, Farzan Fallah, Massoud Pedram
ICCAD
1995
IEEE
129views Hardware» more  ICCAD 1995»
13 years 11 months ago
Activity-driven clock design for low power circuits
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
Gustavo E. Téllez, Amir H. Farrahi, Majid S...
VTC
2006
IEEE
129views Communications» more  VTC 2006»
14 years 1 months ago
A Framework for Automatic Clustering of Parametric MIMO Channel Data Including Path Powers
— We present a solution to the problem of identifying clusters from MIMO measurement data in a data window, with a minimum of user interaction. Conventionally, visual inspection ...
Nicolai Czink, Pierluigi Cera, Jari Salo, Ernst Bo...
HPCA
2005
IEEE
14 years 1 months ago
Heat Stroke: Power-Density-Based Denial of Service in SMT
In the past, there have been several denial-of-service (DOS) attacks which exhaust some shared resource (e.g., physical memory, process table, file descriptors, TCP connections) ...
Jahangir Hasan, Ankit Jalote, T. N. Vijaykumar, Ca...
TCAD
2002
73views more  TCAD 2002»
13 years 7 months ago
System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints
Test scheduling is an important problem in system-on-a-chip (SOC) test automation. Efficient test schedules minimize the overall system test application time, avoid test resource c...
Vikram Iyengar, Krishnendu Chakrabarty