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DATE
2008
IEEE
86views Hardware» more  DATE 2008»
14 years 3 months ago
Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs
Abstract—Wafer-level test during burn-in (WLTBI) has recently emerged as a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, the testi...
Sudarshan Bahukudumbi, Krishnendu Chakrabarty, Ric...
VTS
2008
IEEE
77views Hardware» more  VTS 2008»
14 years 2 months ago
Test-Pattern Ordering for Wafer-Level Test-During-Burn-In
—Wafer-level test during burn-in (WLTBI) is a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, scan-based testing leads to significa...
Sudarshan Bahukudumbi, Krishnendu Chakrabarty
ISQED
2003
IEEE
85views Hardware» more  ISQED 2003»
14 years 1 months ago
Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets
An algorithm for mapping core terminals to System-On-a-Chip (SOC) I/O pins and scheduling tests in order to achieve costefficient concurrent test for core-based designs is present...
Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanja...
ENTCS
2007
116views more  ENTCS 2007»
13 years 8 months ago
Handling Model Changes: Regression Testing and Test-Suite Update with Model-Checkers
Several model-checker based methods to automated test-case generation have been proposed recently. The performance and applicability largely depends on the complexity of the model...
Gordon Fraser, Bernhard K. Aichernig, Franz Wotawa
CORR
2008
Springer
66views Education» more  CORR 2008»
13 years 8 months ago
A Novel Approach to Formulae Production and Overconfidence Measurement to Reduce Risk in Spreadsheet Modelling
Research on formulae production in spreadsheets has established the practice as high risk yet unrecognised as such by industry. There are numerous software applications that are d...
Simon R. Thorne, David Ball, Zoe Lawson