We present an architectural power simulation technique for PLA-based controllers. The contributions of this work are (1) a simple but ecient power characterization of PLAs; and (2...
This paper describes a family of high-speed Finite Impulse Response (FIR) digital filters that have been scaled across three generations of CMOS processes. The processes include c...
Lars E. Thon, Ghavam G. Shahidi, Werner Rausch, Ge...
The objective of entity identification is to determine the correspondence between object instances from more than one database. This paper ezamines the problem at the instance lev...
The use of caches poses a difficult tradeoff for architects of real-time systems. While caches provide significant performance advantages, they have also been viewed as inherently...
Robert D. Arnold, Frank Mueller, David B. Whalley,...
Abstract - We address the problem of automatically verifying large digital designs at the logic level, against high-level specifications. In this paper, we present a methodology wh...