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FPL
2009
Springer
145views Hardware» more  FPL 2009»
14 years 2 months ago
Run-time Partial Reconfiguration speed investigation and architectural design space exploration
Run-time Partial Reconfiguration (PR) speed is significant in applications especially when fast IP core switching is required. In this paper, we propose to use Direct Memory Acce...
Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsc...
CASES
2003
ACM
14 years 1 months ago
A hierarchical approach for energy efficient application design using heterogeneous embedded systems
Several features such as reconfiguration, voltage and frequency scaling, low-power operating states, duty-cycling, etc. are exploited for latency and energy efficient application ...
Sumit Mohanty, Viktor K. Prasanna
VLSID
2008
IEEE
150views VLSI» more  VLSID 2008»
14 years 10 months ago
PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors
Simultaneous Multi-Threading (SMT) processors are becoming popular because they exploit both instruction-level and threadlevel parallelism by issuing instructions from different t...
Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nik...
MASCOTS
2007
13 years 11 months ago
Adaptive Sampling for Efficient MPSoC Architecture Simulation
—Modern micro-architecture simulators are many orders of magnitude slower than the hardware they simulate. The use of multiprocessor architectures for supporting future mobile an...
Melhem Tawk, Khaled Z. Ibrahim, Smaïl Niar
DAC
2007
ACM
14 years 10 months ago
Parameterized Macromodeling for Analog System-Level Design Exploration
In this paper we propose a novel parameterized macromodeling technique for analog circuits. Unlike traditional macromodels that are only extracted for a small variation space, our...
Jian Wang, Xin Li, Lawrence T. Pileggi